Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - serial verilog

Search list

[VHDL-FPGA-Verilog] Verilog

Description: 串口测试程序，用于单片机的串口发送接收数据测试用，-Serial port test program for the microcontroller serial port test sending and receiving data,
Platform: | Size: 181248 | Author: tony | Hits:

[VHDL-FPGA-Verilog] i2c-verilog

Description: 可进行i2c读写操作I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable-it can write and read codes in i2c.I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable
Platform: | Size: 220160 | Author: Jane | Hits:

[VHDL-FPGA-Verilog] FPGA_UART

Description: 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.
Platform: | Size: 3072 | Author: 朱强光 | Hits:

[VHDL-FPGA-Verilog] r232

Description: verilog下fpga串口，波特率115200，与PC通信-Under verilog fpga serial port, baud rate 115200, and PC communication
Platform: | Size: 7168 | Author: 刘欣 | Hits:

[VHDL-FPGA-Verilog] UART_DMA

Description: 基于DE1的nios的串口sdram通信例程-Based on DE1' s nios serial communication routines sdram
Platform: | Size: 11353088 | Author: 李 | Hits:

[VHDL-FPGA-Verilog] Perl_for_CRC

Description: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
Platform: | Size: 90112 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] And-serial-converter

Description: 实现1024位并行输入，32位串行输出的verilog HDL程序 并带有其测试程序-Achieve 1024 parallel input, 32-bit serial output verilog HDL program and with the test procedures and serial converter
Platform: | Size: 3072 | Author: lyj | Hits:

[VHDL-FPGA-Verilog] Verilog-communication-source-code.RAR

Description: 基于Verilog的串口通信源码 ，实现串口通信功能-Verilog source code based on serial communication
Platform: | Size: 954368 | Author: 张洋 | Hits:

[VHDL-FPGA-Verilog] UART_verilog

Description: 带波特率发生器的FPGA_UART串口通信代码，使用ISE10.1综合应用过，通过计算调整两个参数baud_frequcy,baud_limit可适用于多种波特率下的UART传输-With a baud rate generator FPGA_UART serial communication code, use ISE10.1 integrated application before, by calculating the adjusted two parameters baud_frequcy, baud_limit applicable to a variety of baud rate, UART
Platform: | Size: 373760 | Author: rick lee | Hits:

[VHDL-FPGA-Verilog] Serial-debugging

Description: 本文分析RS232 串口通信的原理，介绍Verilog 模块调用的方法-This paper analyzes the principle of the RS232 serial communication, introduction to the Verilog module calls the method
Platform: | Size: 516096 | Author: dltt | Hits:

[VHDL-FPGA-Verilog] UART

Description: verilog写的串口程序，其功能完全最正确，带工程文件-verilog to write the serial program, its function is completely the right, with the project file
Platform: | Size: 433152 | Author: 潘政 | Hits:

[VHDL-FPGA-Verilog] zigbee_sensor

Description: ZigBee无线模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。 在quartusII里面添加uart核，利用串口与主控制机相通信，获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息（其中主控制机与从控制机是通过zigbee协议通信） -ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear quartusII inside, using the serial port with the main control machine communication, access to the sensor from the control on the temperature, humidity, photoresistors, thermistors, and other information (including the main control machine from the control machine by zigbee protocol communications)
Platform: | Size: 1388544 | Author: | Hits:

[OS program] SDRAM_verilog-serial-port

Description: FPGA对sdramd的操作，verilog语言设计！-FPGA SDRAM verilog
Platform: | Size: 44032 | Author: 张民 | Hits:

[VHDL-FPGA-Verilog] verilog-fir

Description: 基于verilog的三种不同方式的fir滤波器 fir1:直接型 fir2：串行DA fir3：并行DA-Fir filter for the verilog three different ways fir1: direct type fir2 of: serial of DA fir3: parallel DA
Platform: | Size: 2048 | Author: | Hits:

[Com Port] FPGA_serial(verilog)

Description: 采用verilog语言编写的关于串口通信的程序，可以参考，希望有所帮助。-Verilog language on the serial communication program can help.
Platform: | Size: 108544 | Author: 张亚洲 | Hits:

[VHDL-FPGA-Verilog] 01-The-basis-of-routine-verilog

Description: 是alter公司开发板上的，一些基础例程，包括串口、LED灯，计数器等等。-Alter development board, some basic routines, including the serial port, LED lights, counters, etc..
Platform: | Size: 28454912 | Author: wangxingbin | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog hdl 写的一个串口程序，编译仿真都已经通过-the verilog hdl write a serial program, compile simulation have passed
Platform: | Size: 10167296 | Author: 林子 | Hits:

[assembly language] UART_RS232(verilog)

Description: /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-/ This module function is to verify that the basic serial communication functions and PC. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepted displayed on the 7-segment LED
Platform: | Size: 600064 | Author: 饕餮小宇 | Hits:

[VHDL-FPGA-Verilog] S8_UART

Description: FPGA串口Verilog程序，用的芯片是xilinx spantan6-The FPGA serial Verilog the program chip with xilinx spantan6
Platform: | Size: 6018048 | Author: 张岩 | Hits:

[Other] UART_verilog

Description: UART串口verilog代码-The UART serial verilog code ..........
Platform: | Size: 2048 | Author: 谭坤 | Hits:
« 1 2 ... 4 5 6 7 8 910 11 12 13 14 ... 34 »

CodeBus www.codebus.net